1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit memories field effect transistors and, more particularly, to non-volatile random access memory (NVRAM) structures and their manufacture.
2. Description of the Prior Art
Semiconductor memory structures are well-known and designs thereof have been integrated at high densities, providing, at the present state of the art, several million dynamic memory cells or tens of thousands of static memory cells on a single chip along with decoding, addressing, sensing and driving circuits allowing data stored therein to be changed at will. Such memories and the speed of access they allow are indispensable to support the high speed of digital processors presently available. However, the maintenance of storage states of the cells requires at least constant application of at least stand-by power and, for dynamic memory cells, periodic refreshing. Since storage states are not otherwise maintained, such memories are referred to as being volatile.
So-called read only memories (ROMs) are not volatile but the contents thereof cannot be changed. ROMs are, nevertheless, useful for personalization of electronic devices and storage of basic operational programming of processors since they generally support very high speed access. Otherwise, other storage media such as magnetic disks, bubble memories and the like have generally been used for non-volatile storage of data when the capability of changing the data must be provided even if access to the data is generally much slower.
To partially overcome the slower access time of other storage devices and media, various caching schemes have been developed which are, in general, quite effective to support the function of available high speed processors. Nevertheless, delays may be encountered when data required by the processor is not present in the cache, reducing predictability of task completion time. Further, use of a cache does not provide freedom from other characteristics of the storage medium utilized such as the mechanical vulnerability of magnetic disk drives to wear, impact, vibration and the like. Expansion of cache capacity to avoid significant delays due to the number of cache misses which may be encountered requires a degree of processing overhead as well as the time to access the desired amount of information from main storage, particularly as compared with processor cycle time.
Non-volatile semiconductor structures are known and have been referred to as programmable read only memories (PROMs) in view of the fact that data can be written or programmed therein rather than being established during the fabrication of the device. More recently, designs of PROMs have allowed data to be changed by erasure and rewriting. These structures generally employ electron tunnelling phenomena through a thin dielectric layer. Each tunnelling operation, however, causes a finite amount of damage to the dielectric and the number of write and erase cycles which can be performed before failure has been limited. Accordingly, these devices have been referred to as electrically erasable programmable read only memories (EEPROMs or flash EEPROMs if all cells of a partition are simultaneously erased) since they are intended for applications in which data will be changed only rarely.
More specifically, memory cells of EEPROMs generally include a structure similar to that of a field effect transistor but having an insulated floating gate electrode to which a control gate is capacitively coupled. Thus, a low voltage on the control gate together with presence or absence of charge stored on the floating gate can allow the reading of the cell in accordance with the resultant conductance of the transistor while higher voltages on the control gate cause hot electron injection or tunnelling of electrons from the conduction channel to or from the floating gate for writing or erasure of the EEPROM cell.
Very recently, some electron tunnelling mechanisms (e.g. Fowler-Nordheim tunnelling) have been exploited in which the damage to the dielectric during write and/or erase operations is very much reduced. Together with improvements in dielectric quality and distribution of write and erase operations over the memory array, the number of write and erase operations which can be accomplished before device failure has become sufficient to the expected service lifetime of computers and other electronic apparatus in which such memories may be employed. Thus, such devices can be used much in the manner of random access memories and have come to be referred to as non-volatile random access memories (NVRAMs). The number of storage cells which may be provided on a single chip has also become comparable to that of static RAMs and approaches that of dynamic RAMs. The non-volatile random access memories (NVRAMs) nomenclature thus also connotes the potential further applications now possible with the practical removal of limitations on the number of write/erase cycles which can be performed without significant degradation of the tunnelling oxide.
It should be understood, however, that the basic structure of the NVRAM cell has remained effectively unchanged from the structure of an EEPROM cell although a different tunnelling mechanism may be exploited and the operating parameters correspondingly altered. The structure of a NVRAM cell is relatively complex and critical and development of high manufacturing yields consistent with high integration density has proven difficult. Moreover, the additional applications for which modern NVRAMs are currently suitable has increased the need for reduction of NVRAM cell size and increased integration density.
Tunnelling effects on which NVRAMs continue to rely for write and erase operations, however, requires a higher voltage than is required for read operations while high integration density requires small sizes of the memory cells. To avoid breakdown, latch-up and other known types of malfunctions, isolation structures are generally required between NVRAM cells and write and erase voltages are kept as low as possible consistent with correct operation. By the same token, narrow operating margins for write and erase voltages together with isolation structures such as shallow trench isolation (STI) and recessed oxide isolation (ROX), both of which employ an insulator within the substrate and may also extend above the substrate surface, have required formation of the floating gate and the control gate along the sidewalls of the isolation structure in order to develop an adequate so-called coupling ratio of the capacitances of the control and floating gates. In general, the floating gate is made to overlap a portion of the ROX or STI, covered with a blanket layer of interpoly oxide and a doped polysilicon gate layer applied thereover and patterned.
Since the control gate must extend over the floating gate where the floating gate, in turn, extends over an isolation structure, severe large step topography is unavoidable in the control gate and the interpoly oxide, as well. This step is sufficiently steep to allow formation of a sidewall during subsequent routine processing (if not prevented by additional process steps) or breaks in the silicide of which the control gate or a connection thereto may be partially comprised (e.g. overlaying a doped polysilicon layer with a refractory metal silicide having low sheet resistance to form a so-called polycide connector). Breaks in the control gate silicide severely compromise manufacturing yield since a control gate generally overlies and provides access to a plurality of NVRAM cells and a break thus isolates and prevents access to cells beyond the break in the control gate.
Nevertheless, it should be understood that the severe topography described above has generally been exploited to advantage in developing an adequate coupling ratio of capacitance of the control gate to that of the floating gate. A minimum coupling ratio must be maintained so that the capacitive voltage divider can adequately raise or lower the potential of the floating gate for tunnelling to occur to write and erase the NVRAM cell. There is thus a trade-off between the coupling ratio and the voltage which must be applied for reliable writing and erasure and, consequently, the size and spacing of other structures to avoid breakdown, latch-up and the like and, ultimately, between manufacturing yield and the integration density which can be achieved. Accordingly, some degree of compromise of manufacturing yield, integration density and design optimization has been tolerated in previous designs which has increased the cost and limited production and application of high density NVRAMs both at the package level and in various computers and other electronic apparatus.
So-called damascene processes for semiconductor manufacture are now familiar to those skilled in the art, particularly for the reliable formation of highly robust conductors at fine pitch. Essentially, a generalized damascene process comprises forming a groove or recess of desired dimensions or pattern in a substrate or semiconductor layer, filling the groove or recess by the deposition of a blanket layer of material and planarizing the blanket layer back to the original surface of the substrate or semiconductor layer. The planarization thus serves to separate the layer into a plurality of formations, such as conductors, in accordance with the original shape of the groove(s) or recess(es). During and after the planarization, the material in the grooves or recesses is supported on all sides, resulting in a highly robust structure even when comprised of very soft metals or other materials. Since the grooves or recesses are ideally formed lithographically beginning with a highly planar surface, high lithographic resolution and fine pitch are thus supported. Further, the planarization after blanket layer deposition and filling of the grooves or recesses provides a highly planar surface on which further lithographic processes may be carried out with high accuracy and resolution.
However, at the present state of the art, due to difficulties with trench filling, throughput of planarization processes and the like, damascene processes are generally limited to the formation of conductors in which the advantages of robustness and fine pitch are pronounced and not otherwise obtainable. Damascene processes are not widely used for device (e.g. transistors and capacitors) construction within a substrate or layer or with materials which do not reliably fill high aspect ratio grooves or recesses. For high manufacturing yields, surface formation processes such as deposition and etching or patterned implantation are generally preferred for high manufacturing yields in the formation of specific devices integrated on a chip.